Design Engineering Manager - Bangalore, India

Originally posted 7 August 2024 by the employer — open 764 days.

Work on High Speed SERDES Test chips.

About the role

This role involves leading pre-silicon Physical Layer Electrical Validation infrastructure development and post-silicon validation efforts. You will primarily focus on Cadence's High Speed SERDES Test chips.

What you'll do

• Lead pre-silicon Physical Layer Electrical Validation infrastructure development.
• Lead post-silicon validation efforts on High Speed SERDES Test chips.
• Design hardware and software architecture for testing test chips, including test PCBs and controlling FPGA platforms.
• Define test plans for rigorously testing compliance to Physical Layer Electrical specifications.
• Implement defined tests and generate high quality test reports.

What you'll need

• 6-10 years (BTech) or 4-8 years (MTech) of experience in Post-Silicon Physical Layer Electrical Validation.
• Deep Physical Layer electrical validation experience on at least one High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO.
• Strong hands-on experience using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT).

Nice to have

• Experience managing small teams (at least 2 members).
• Experience leading complete post-silicon validation efforts for at least one full project.
• 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping.
• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
• Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL.
• Experience conducting hiring interviews and mentoring new hires.
• Passion for analog and digital electronic circuit design aspects as well as signal processing related aspects.

Skills: Physical Layer Electrical Validation, High Speed SERDES, Test chips, signal integrity, timing closure, chip-to-chip interfaces