Design Engineer - STA - USA-Colorado-Fort Collins-4380 Ziegler Road, United States
$109,700 - $175,500 USD yearly
Originally posted 1 September 2026 by the employer — open 15 days.
About the role
This STA Engineering role focuses on chip-level timing architecture, analysis, and closure for advanced ASICs. The position provides hands-on experience with 3 nm and smaller process nodes for AI, computing, and networking SoCs.
What you'll do
- Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
- Perform static timing analysis (STA) using industry-standard tools like Synopsys PrimeTime or Cadence Tempus.
- Define and execute timing signoff methodologies, including process corners, derates, and uncertainties.
- Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.
- Automate timing flows and analysis using Tcl and scripting languages such as Perl or Python.
- Analyze and debug timing violations, signal integrity issues, and clock network challenges.
What you'll need
- BS in Electrical or Computer Engineering with 8+ years of relevant experience, or MS with 6+ years of relevant experience.
- Deep understanding of VLSI design principles and ASIC physical design fundamentals.
- Working knowledge of PLLs, clock network design, flip-flops, latches, and memories.
- Proficiency in timing constraint creation, debugging, and validation.
- Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.
- Familiarity with setup/hold analysis, multi-mode multi-corner (MMMC) timing, and ECO convergence.
Nice to have
- Proficiency in Python, Perl, or Ruby.
- Hands-on experience with Synopsys and/or Cadence STA tools.
- Exposure to advanced STA techniques, including POCV/SOCV/LVF, PBA, and SPICE correlation.
- Knowledge of timing libraries (CCS/ECSM/NLDM) and multi-input switching (MIS) effects.
- Technical leadership, mentoring, and initiative in methodology improvements.
Skills: static timing analysis, STA, timing closure, Synopsys PrimeTime, timing constraints, ECOs
This role has been open 15 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
596
|
Median days open
57 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (596 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 38 | 596 |
| Open roles in the wider Physical Implementation family | 46 | 1370 · 105 employers |
| Median days open | 66 d | 57 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: static timing analysis, STA, timing closure, Synopsys PrimeTime, timing constraints, ECOs
Who's hiring in this category
- Qualcomm · 102 open roles · median 41 d
- Broadcom (this employer) · 39 open roles · median 66 d
- NVIDIA · 39 open roles · median 41 d
- AMD · 34 open roles · median 40 d
- Synopsys · 28 open roles · median 56 d
- Renesas Electronics · 25 open roles · median 43 d
How we counted: 596 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.