Design Engineer II - Bangalore, India
Analog & Mixed-Signal Design
Originally posted 17 July 2024 by the employer — open 785 days.
About the role
This role focuses on Post-Silicon Physical Layer Electrical Validation for High-speed SERDES protocols.
What you'll do
- Perform Post-Silicon Physical Layer Electrical Validation.
- Utilize lab equipment such as Oscilloscopes, Network Analyzer, and Bit Error Rate Tester (BERT).
- Validate High-speed SERDES protocols like PCIe, USB, DP, ethernet, SRIO, JESD204, or DDRIO.
What you'll need
- 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation.
- Deep Physical Layer electrical validation experience on at least one High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, or DDRIO.
- Strong hands-on experience in using lab equipment such as Oscilloscopes, Network Analyzer, and Bit Error Rate Tester (BERT).
Nice to have
- Experience managing small teams (at least 2 members and above).
- Experience leading the complete post silicon validation efforts for at least one full project.
- 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping.
- Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
- Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL.
- Experience conducting hiring interviews and mentoring new hires.
- BE/BTech/ME/MTech or equivalent.
Skills: Post-Silicon Validation, SERDES, PCIe, USB, Oscilloscopes
Market context
This role has been open 169 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 19 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Post-Silicon Validation, SERDES, PCIe, USB, Oscilloscopes
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems (this employer) · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.