DDR PHY System Design Engineer (San Diego, US)
$140,000 - $210,000 USD yearly
Originally posted 28 April 2026 by the employer — open 135 days.
About the role
This role involves the system design, building, and testing of high-speed, high-performance, and low-power DDR PHYs. The DDR PHYs are targeted for 5G, AI/ML, compute, and automotive applications.
What you'll do
- Analyze and own DDR PHY system and architecture.
- Develop system timing budgets for on-die and off-chip implementations.
- Lead and deliver solutions for product needs.
What you'll need
- 5-10 years in DDR PHY system design/architecture.
- Strong knowledge of JEDEC DDR standards (LPDDR/PCDDR/HBM) and their implication to DDR PHY system design/architecture.
- Strong knowledge of link-budgets and trainings.
- Bachelor's degree in Electrical Engineering.
Nice to have
- Knowledge of signal integrity and power delivery for server products.
- Knowledge of latest process technology nodes and mixed-signal designs.
- Solid understanding of design-for-yield and production challenges in high-speed links.
- Unix/Perl/TCL scripting.
Skills: DDR PHY, DDR standards, link-budgets, high-speed interface, signal integrity, power integrity
This role has been open 133 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 17 | 217 |
| Median days open | 74 d | 91 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: DDR PHY, DDR standards, link-budgets, high-speed interface, signal integrity, power integrity
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm (this employer) · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.