DDR Interface Evaluation Leader - Kodaira, Japan
Originally posted 2 April 2026 by the employer — open 161 days.
About the role
This role leads the technical execution of DDR interface evaluation for automotive SoCs, focusing on ensuring reliable operation through silicon-level evaluation and root-cause analysis.
What you'll do
- Lead the technical execution of DDR interface evaluation for automotive SoCs (R-Car series).
- Drive silicon and board-level evaluation, margin analysis, stress testing, and compliance for DDR interfaces.
- Define evaluation strategy, design test items and conditions, and consolidate evaluation results.
- Collaborate with design teams, SoC teams, and IP vendors to perform root-cause analysis and plan countermeasures.
- Provide technical leadership to evaluation and design members, clarifying evaluation flow and decision criteria.
What you'll need
- Hands-on experience in evaluation or verification of DDR interfaces (e.g., LPDDR4/4X/5).
- Experience in issue analysis, root-cause investigation, and countermeasure discussion based on margin testing and stress evaluation.
- Ability to organize evaluation results and conduct technical discussions with design teams and stakeholders.
- Knowledge or experience related to analog behavior and characteristics relevant to DDR interfaces (e.g., DDR PHY, PLL, jitter, noise, SI/PI, power integrity).
- Ability to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors.
Skills: DDR interface evaluation, LPDDR4X/5/5X/6, DDR PHY, memory controller, silicon and board-level evaluation, root-cause analysis
This role has been open 160 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 8 | 217 |
| Median days open | 160 d | 91 d (+69 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: DDR interface evaluation, LPDDR4X/5/5X/6, DDR PHY, memory controller, silicon and board-level evaluation, root-cause analysis
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.