DDR Bench Characterization Engineer
$94,200 - $141,200 USD yearly
Originally posted 6 May 2026 by the employer — open 127 days. Relisted by the employer on 20 August 2026.
About the role
This role involves developing test solutions for highly integrated SOCs, specifically defining and executing characterization for LP-DDR & PC-DDR Subsystem components.
What you'll do
- Define and execute test methodologies and characterization for LP-DDR & PC-DDR Subsystem components.
- Develop and execute characterization plans for High Speed IPs to optimize design parameters and validate electrical compliance.
- Drive first silicon bring-up and debug to qualify designs fabricated at external foundries.
- Perform parametric analysis of silicon behavior over process, voltage, and temperature conditions.
- Develop and automate test scripts, measurement procedures, and data processing flows for silicon evaluation.
- Assist in hardware design and debug of power integrity (PI) and signal integrity (SI) issues related to package and board design.
What you'll need
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field.
- 1 year of experience in hardware engineering or related work experience (or Master's degree in related field).
- Experience with Python/C# for test automation.
- Strong understanding of VLSI technologies, CMOS analog and digital integrated circuits, mixed-signal, and semiconductor physics.
- Strong ASIC device level characterization skills.
- Strong problem solving & debugging skills.
Nice to have
- Master's Degree in Electrical/Computer Engineering or related field.
- Knowledge of High-Speed test and characterization including eye diagram characteristics, differential signals, jitter analysis, signal integrity.
- Familiarity with DDR 2/3/4/5, LPDDR 2/3/4/5 protocol, interface, IO receiver/transmitter, timing diagrams, and device specifications.
- Hands-on experience with lab equipment such as Oscilloscopes, TDRs/VNAs, J-BERT, and power measurement tools.
- Familiarity with Board Design concepts (Schematic reviews, Layout best practices).
- Knowledge in test automation development/scripting/debugging.
- System level knowledge.
Skills: DDR, Mixed Signal PHY IP, IO circuits, High-Speed IP characterization, silicon bring-up, signal integrity
This role has been open 126 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 17 | 217 |
| Median days open | 74 d | 91 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: DDR, Mixed Signal PHY IP, IO circuits, High-Speed IP characterization, silicon bring-up, signal integrity
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm (this employer) · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.