CPU Server Physical Design Clock Engineer - Austin, Texas, United States of America, United States
$148,300 - $222,500 USD yearly
Originally posted 16 June 2026 by the employer.
About the role
As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block level, and top level physical design teams to create clocking solutions for CPUs.
What you'll do
- Work with design teams to understand, implement, and validate CPU clocking. - Drive overall clock generation and distribution methodology of the CPU. - Work with CAD and block level designers to implement clocking techniques for optimizing skew and power. - Perform jitter analysis and measurements, providing feedback on key fixes to block level and top level physical design engineers.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of hardware engineering experience (or Master's degree with 3+ years, or PhD with 2+ years). - Experience in all aspects of construction and analysis of low skew and low power clock generation and distribution. - Experience in clock H-tree, mesh, spines, and CTS implementations. - Understanding of device physics, RC delay, and electrical aspects. - Proficiency in SPICE simulation and analysis for circuit design and verification.
Nice to have
- MS in Electrical Engineering with 8 years of practical experience. - Experience in chip physical design, standard cell optimizations, and clock construction. - Experience defining clock methodology across multiple designs. - Experience in deep submicron process technology nodes. - Proficiency in PLL specifications, clock skew estimation, and jitter measurements.
Skills: CPU clocking, clock generation and distribution, skew and power optimization, jitter analysis, physical design
This role has been open 131 days — well above the 65-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 123 | 673 |
| Open roles in the wider Physical Implementation family | 170 | 1491 · 109 employers |
| Median days open | 48 d | 65 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: CPU clocking, clock generation and distribution, skew and power optimization, jitter analysis, physical design
Who's hiring in this category
- Qualcomm (this employer) · 124 open roles · median 48 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 17 d
- Synopsys · 37 open roles · median 39 d
- NVIDIA · 36 open roles · median 67 d
- Broadcom · 35 open roles · median 104 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.