CPU Physical Design Engineer - Texas, Austin, United States
$105,650 - $200,340 USD yearly
Originally posted 8 August 2026 by the employer. Relisted by the employer on 9 October 2026.
About the role
This role performs physical design implementation of custom CPU designs from RTL to GDS to deliver design databases ready for manufacturing.
What you'll do
- Execute the full CPU physical design flow, including synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, power and clock distribution, and noise analysis. - Conduct verification and signoff encompassing formal equivalence verification, static timing analysis, reliability verification, power integrity, layout verification, DRC/LVS, and electrical rule checking. - Optimize CPU blocks and partitions to meet product-level power, frequency, and area targets. - Address structural and physical design challenges, including physical clock design, timing closure, multiple power domain analysis, structured placement, and DFT. - Collaborate with logic, circuit, architecture, and design automation teams, as well as EDA vendors to enhance tool capabilities. - Contribute to physical design methodologies and flow automation.
What you'll need
- Bachelor's degree in Computer Engineering, Electrical Engineering, or related field with 6+ years of relevant experience, or a Master's degree (or higher) with 4+ years of relevant experience. - 4+ years of experience in synthesis of a digital logic block or partition. - At least 1 completed tapeout on advanced technologies. - 4+ years of experience with integrated circuit design tools (such as Synopsys or Cadence) across logic synthesis, place and route, static timing analysis, and design closure. - 4+ years of experience with PV convergence, including static timing and power analysis. - 4+ years of experience in chip physical design verification (formal equivalence, electrical rules, DRC/LVS, noise flow) and scripting with TCL.
Nice to have
- 8+ years of tapeout experience. - Knowledge of physical design practices for floorplanning, routing techniques, and clock distribution. - Knowledge of static timing analysis, noise analysis, reliability verification techniques, and RTL to GDS methodologies with formal equivalence. - Experience performing CPU-level timing analysis, generating and verifying timing constraints, and resolving timing violations for CPU cores. - Experience collaborating with clocking and full-chip design teams on timing fixes, power delivery, clocking, and partitioning.
Skills: physical design implementation, RTL to GDS, place and route, static timing analysis, design closure
This role has been open 77 days — well above the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 40 | 673 |
| Open roles in the wider Physical Implementation family | 63 | 1489 · 109 employers |
| Median days open | 16 d | 64 d (−48 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical design implementation, RTL to GDS, place and route, static timing analysis, design closure
Who's hiring in this category
- Qualcomm · 123 open roles · median 47 d
- AMD · 64 open roles · median 27 d
- Intel Corporation (this employer) · 40 open roles · median 16 d
- Synopsys · 37 open roles · median 38 d
- NVIDIA · 36 open roles · median 66 d
- Broadcom · 34 open roles · median 103 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.