CPU Integration CAD Engineer - Santa Clara, California, United States of America
$167,100 - $250,700 USD yearly
Originally posted 8 May 2026 by the employer.
About the role
As a CPU Integration CAD Engineer at Qualcomm, you will build and support implementation tools and flows for custom CPU designs.
What you'll do
- Work closely with cross-functional teams including CPU physical design, CPU and SOC integration, Technology, and Central CAD. - Develop, integrate, and release flows and methodologies for floorplanning (power planning, pin placement) or PDV analysis (DRC/LVS/antenna). - Architect, maintain, and support implementation flows, resolving project-specific issues. - Work with EDA vendors to define roadmaps and resolve tool issues.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant engineering experience (or Master's degree and 3+ years, or PhD and 2+ years).
Nice to have
- Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Science. - Ten years of hands-on experience in development of high-performance chips in a design or CAD role. - High level of programming proficiency in Python and Tcl, with knowledge of data structures and algorithms. - Experience with automation. - Strong user of PNR tool Innovus or PDV Calibre tool or equivalent. - Experience with physical design tasks ranging from place-and-route, analysis, timing sign-off, and PDV. - Experience with advanced technology nodes (5nm or lower).
Skills: floorplanning, PDV analysis, Innovus, Calibre, timing sign-off
This role has been open 200 days — well above the 71-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
71 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (696 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 696 |
| Open roles in the wider Physical Implementation family | 170 | 1491 · 109 employers |
| Median days open | 76 d | 71 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: floorplanning, PDV analysis, Innovus, Calibre, timing sign-off
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 152 d
- Synopsys · 62 open roles · median 43 d
- Micron Technology · 44 open roles · median 52 d
- GlobalFoundries · 39 open roles · median 26 d
- Qualcomm (this employer) · 39 open roles · median 76 d
- Keysight Technologies · 34 open roles · median 79 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.