Chip Lead: Analog & Mixed-Signal Layout Engineer - Bangalore, India

Originally posted 15 October 2025 by the employer — open 330 days.

About the role

This role is for a senior analog & mixed-signal layout designer responsible for the layout of high performance, high speed CMOS data converters.

What you'll do

• Perform layout of high performance, high speed analog blocks such as ADC, DAC, PLL, and SERDES.
• Apply analog layout techniques including common centroid, interdigitation, shielding, dummy devices, and EM aware routing on critical blocks.
• Utilize VXL compliant methodology.
• Conduct various physical verification checks including DRC, LVS, DFM, ERC, EM, IR.
• Lead project activities.

What you'll need

• 10+ years experience in high performance analog layout in advanced CMOS process nodes.
• Experience with layouts of high performance and high speed analog blocks (such as ADC, DAC, PLL, and SERDES).
• Expertise in analog layout techniques such as common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block.
• Familiarity with VXL compliant methodology.
• Familiarity in various physical verification checks DRC, LVS, DFM, ERC, EM, IR.
• Ability to define and adhere to schedule and methodology.
• Strong social skills and teamwork.

Nice to have

• Layout Automation using SKILL/PERL/Python.

Skills: analog layout, advanced CMOS process, ADC, DAC, PLL, SERDES layout, DRC, LVS, DFM, ERC, EM, IR, common centroid, interdigitation