Chip Lead: Analog & Mixed-Signal Layout Engineer - Milpitas, United States

Originally posted 16 October 2025 by the employer — open 328 days.

About the role

This role involves the layout of high performance, high speed CMOS data converters in foundry CMOS process nodes including 2nm, 3nm, 5nm, 6nm, 7nm, 16nm, and 28nm.

What you'll do

• Lead layout projects for high performance analog designs.
• Perform layout of high performance and high speed analog blocks such as ADC, DAC, PLL, and SERDES.
• Apply analog layout techniques including common centroid, interdigitation, shielding, dummy devices, and EM aware routing.
• Ensure VXL compliant methodology is followed.
• Conduct physical verification checks such as DRC, LVS, DFM, ERC, EM, and IR.

What you'll need

• 10+ years experience in high performance analog layout in advanced Finfet/CMOS process nodes.
• Experience with layouts of high performance and high speed analog blocks (ADC, DAC, PLL, SERDES).
• Experience with analog layout techniques such as common centroid, interdigitation, shielding, dummy devices, EM aware routing.
• Familiarity with physical verification checks: DRC, LVS, DFM, ERC, EM, IR.

Nice to have

• Layout Automation using SKILL/PERL/Python.

Skills: analog layout, advanced Finfet/CMOS process, ADC, DAC, PLL, SERDES layout, DRC, LVS, DFM, ERC, EM, IR, common centroid, interdigitation