Chip Design Engineer - Palo Alto, United States
Originally posted 10 September 2026 by the employer.
About the role
This role owns implementation and signoff across the physical design flow, from synthesis through tapeout, delivering closure for complex blocks at advanced nodes.
What you'll do
- Contribute to synthesis, DFT insertion, floorplanning, PDN design, placement, CTS, routing, and all electrical, timing, and physical signoff. - Own timing, power, and physical closure of complex, PPA-critical blocks in advanced nodes, driving multi-mode multi-corner timing convergence, EM/IR signoff, and DRC/LVS closure through final ECOs and tapeout. - Partner cross-functionally on chip design infrastructure and automation, optimization techniques and goals, and design improvement strategies.
What you'll need
- BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field. - 5+ years of hands-on physical design experience spanning synthesis, floorplanning, PDN, placement, CTS, routing, STA, extraction, power/EM/IR analysis, physical verification, LEC, and ECO, including architecting hierarchical flows both top-down and bottom-up. - Day-one fluency in at least one production implementation and signoff stack with chip design tools, along with strong Tcl and Python scripting skills. - Track record of successful chip design and tapeout, having owned closure of complex blocks, subsystems, or full chips through complete signoff in advanced technology nodes for silicon shipped to production.
Nice to have
- Masters or PhD in EE, CE, CS, or a related field, with a focus on VLSI, physical design, or EDA/CAD algorithms. - Expertise in high-performance compute silicon (e.g., ML accelerators, CPUs, GPUs, or large SoCs), including multi-voltage domain (UPF) design and 2.5D/3D integration with bump/RDL planning. - Publications at major conferences (e.g., DAC, ICCAD, ISPD, DATE) demonstrating research strength in physical design or AI for chip design.
Skills: physical design, synthesis, STA, floorplanning, tapeout, PPA
This role has been open 1 day — well below the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ricursive Intelligence | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 682 |
| Open roles in the wider Physical Implementation family | 4 | 1530 · 112 employers |
| Median days open | 1 d | 66 d (−65 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: physical design, synthesis, STA, floorplanning, tapeout, PPA
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.