Chief Memory Chip Design Engineer & Architect
Originally posted 30 October 2026 by the employer.
About the role
This role owns end-to-end memory product architecture from concept through silicon qualification, setting power, performance, and area trade-offs across design, process, and product engineering.
What you'll do
- Define the memory subsystem architecture, including array, periphery, I/O, redundancy, test, and reliability, translating product requirements into design specifications.
- Drive floorplan and physical architecture covering array efficiency, periphery partitioning, power delivery, and die-level signal integrity.
- Own the multi-generation roadmap addressing node migration along with density and performance scaling.
- Arbitrate cross-functional trade-offs across process integration, circuits, DFT, packaging, and controller/firmware interfaces.
- Own the design methodology and EDA/CAD strategy across tools, flows, vendors, and licenses.
- Represent the architecture to executives, customers, foundry partners, and standards bodies while mentoring senior and principal engineers.
What you'll need
- MS/PhD in EE, CE, or a related field.
- 15+ years in memory or mixed-signal IC development, with 5+ years as an architect or chief engineer.
- Track record of owning 2+ memory products from architecture through production silicon.
- Deep advanced CMOS FinFET expertise spanning layout, variability, reliability, and DFM.
- Breadth across memory architectures (DRAM, NAND/NOR, SRAM, emerging NVM) with depth in at least one area.
- Direct experience with Cadence and Synopsys custom and digital flows through full-chip sign-off.
- Experience owning EDA/CAD strategy and directing multi-site programs through technical influence.
Nice to have
- Experience with embedded memory IP integration into SoCs and memory-controller co-design.
- Direct foundry engagement on PDKs, test chips, and DTCO.
- Emerging NVM architecture experience, active JEDEC participation, patents, or publications.
Skills: memory architecture, FinFET, DRAM, NAND, floorplan
This role has been open 0 days — well below the 71-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
322
|
Median days open
71 d
|
Category median salary (all employers)
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Western Digital | All employers we track in this specialty (322 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 322 |
| Median days open | 4 d | 71 d (−67 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: memory architecture, FinFET, DRAM, NAND, floorplan
Who's hiring in this category
- Micron Technology · 170 open roles · median 82 d
- Synopsys · 32 open roles · median 70 d
- Qualcomm · 19 open roles · median 91 d
- SanDisk · 17 open roles · median 57 d
- Broadcom · 16 open roles · median 71 d
- Arm Holdings · 7 open roles · median 2 d
How we counted: 322 open Memory Design (Memory Design) roles from 30 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.