CAD and PPA Methodology Engineer
$161,800 - $242,600 USD yearly
Originally posted 17 November 2025 by the employer.
About the role
As a member of the Graphics team, you will develop flows, methodologies, and algorithms to improve power, performance, and area (PPA) on GPU cores while collaborating with microarchitecture design and implementation teams. The work spans the ASIC design flow from RTL to GDS, including synthesis, static timing analysis, formal verification, physical design, and ECO generation.
What you'll do
- Develop new flows, methodologies, and algorithms to drive PPA improvements into GPU cores. - Collaborate with design, technology, power, implementation, sign-off, and post-silicon teams to manage tradeoffs across power, performance, and area. - Support ASIC implementation from RTL to GDSII, covering synthesis, static timing analysis, formal verification, and physical design. - Manage design constraints for power, timing, clocking, and interfaces. - Perform clock tree analysis and optimization, alongside ECO generation and verification for functional and timing fixes. - Identify target areas for design flow and process improvements across semi-custom design pipelines.
What you'll need
- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with 4+ years of hardware, software, or systems engineering experience (or Master's degree with 3+ years, or PhD with 2+ years). - Basic understanding of RTL design and ASIC design flow from RTL to GDS, such as synthesis, static timing analysis, formal verification, physical design, and ECO generation. - Understanding of Verilog and System-Verilog languages. - Knowledge of design constraint management for power, timing, clocking, and interfaces. - Familiarity with formal verification for RTL-netlist and netlist-netlist checks.
Nice to have
- 5-7 years of experience developing methodologies for PPA improvement. - Hands-on experience with EDA tools including Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower, PrimeTime, and Prime Closure. - Script writing experience in UNIX shell, Python, Perl, and/or TCL. - Experience with implementation and delivery of GPU cores from RTL to GDSII. - Experience with RTL synthesis using physically aware tools.
Skills: PPA methodology, Synopsys Fusion Compiler, PrimeTime, Python, Perl, TCL
This role has been open 200 days — well above the 71-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
71 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (696 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 696 |
| Open roles in the wider Physical Implementation family | 170 | 1491 · 109 employers |
| Median days open | 76 d | 71 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: PPA methodology, Synopsys Fusion Compiler, PrimeTime, Python, Perl, TCL
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 152 d
- Synopsys · 62 open roles · median 43 d
- Micron Technology · 44 open roles · median 52 d
- GlobalFoundries · 39 open roles · median 26 d
- Qualcomm (this employer) · 39 open roles · median 76 d
- Keysight Technologies · 34 open roles · median 79 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.