$121,800 - $182,600 USD yearly
Originally posted 13 November 2026 by the employer.
About the role
This role is responsible for the complete verification lifecycle from system-level concept to tape out and post-silicon support. Technical scope includes comprehensive pre-silicon test planning, testbench development using SystemVerilog-UVM, coverage development, assertion model development, and formal verification for digital power IPs.
What you'll do
- Develop pre-silicon test plans, UVM testbenches, coverage models, and assertion models for digital power IPs.
- Execute formal verification (property checking) and deploy power-aware UPF verification flow and methodology.
- Develop automation to improve verification efficiency.
- Define, model, design, optimize, verify, validate, and document IP (block/SoC) development.
- Collaborate across software architecture and hardware architecture teams to execute implementation strategies meeting system requirements.
- Write detailed technical documentation for EDA/IP/ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, integration, or related work experience (or Master's with 1+ year, or PhD).
- Experience with ASIC design and verification tools, techniques, and methodology.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 3 years of ASIC design, verification, validation, integration, or related work experience.
- 2 years of experience with architecture and design tools.
- 2 years of experience with scripting tools and programming languages.
- 2 years of experience with design verification methods.
Skills: ASIC, verification, IP, EDA, SystemVerilog
More semiconductor jobs: Qualcomm jobs · Verification engineer jobs · San Diego jobs
First seen in our index 0 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1395
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1395 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 138 | 1395 |
| Open roles in the wider Digital Design & Verification family | 444 | 3618 · 122 employers |
| Median days since first seen | 52 d | 59 d (+7 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: ASIC, verification, IP, EDA, SystemVerilog
Who's hiring in this category
- Qualcomm (this employer) · 129 open roles · median 52 d
- NVIDIA · 109 open roles · median 73 d
- Apple · 107 open roles · median 16 d
- AMD · 82 open roles · median 63 d
- Synopsys · 80 open roles · median 57 d
- SiFive · 57 open roles · median 71 d
How we counted: 1395 open Design Verification (Design Verification) roles from 100 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.