ASIC Physical Design, Principal Engineer
Drive RTL-to-GDSII physical integration and timing closure for 112G and 224G PAM4/6 SerDes IP at 16nm and below.
Originally posted 5 November 2026 by the employer.
About the role
As a Principal Engineer in ASIC Physical Design, you will own physical integration for high-speed interface IP from floorplanning through signoff. The role focuses on 56G, 112G, and 224G PAM4/6 SerDes IP across advanced FinFET nodes.
What you'll do
- Own physical integration for SerDes IP from floorplanning through GDSII, including timing closure, power optimization, and signoff at 16nm and below.
- Drive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 SerDes across FinFET nodes, collaborating with front-end, analog, and CAD teams.
- Develop and validate timing constraints, clock architectures, and low-power design techniques to meet customer PPA targets.
- Lead customer engagements on physical integration topics, including SOC-level integration planning, constraint delivery, and tapeout support.
- Build and improve design methodologies, automation scripts using Perl, Tcl, or Python, and flows to enhance delivery predictability.
- Debug and resolve complex analog-digital interface issues in collaboration with analog design and verification teams.
What you'll need
- MSEE with 10+ years or BSEE with 12+ years of digital or physical design experience, with recent contributions to project tapeouts.
- Deep hands-on experience with the full RTL-to-GDSII flow, including chip-level integration, timing closure, and physical signoff.
- Experience with advanced FinFET nodes (TSMC 16nm or below), including low-power design techniques and process-specific challenges.
- Strong understanding of timing constraint development, clock architecture, and design techniques to meet power and area targets.
- Solid understanding of digital and mixed-signal verification flows, SOC integration challenges, and analog-digital interface considerations.
- Scripting and automation skills in Perl, Tcl, or Python with a methodology-driven approach to design and CAD flows.
Skills: physical design, RTL-to-GDSII, timing closure, SerDes, FinFET, PPA
More semiconductor jobs: Synopsys jobs · Physical design jobs · Sunnyvale jobs
This role has been open 0 days — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
720
|
Median days open
58 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (720 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 44 | 720 |
| Open roles in the wider Physical Implementation family | 115 | 1611 · 116 employers |
| Median days open | 38 d | 58 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: physical design, RTL-to-GDSII, timing closure, SerDes, FinFET, PPA
Who's hiring in this category
- Qualcomm · 105 open roles · median 59 d
- AMD · 64 open roles · median 39 d
- Broadcom · 49 open roles · median 39 d
- NVIDIA · 45 open roles · median 80 d
- Synopsys (this employer) · 43 open roles · median 38 d
- Intel Corporation · 32 open roles · median 29 d
How we counted: 720 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.