ASIC Methodology Engineer
$153,200 - $229,800 USD yearly
Originally posted 20 May 2026 by the employer.
About the role
As a member of the DTECH Methodology team, you will work closely with core and SOC teams to enable a design analytics platform. The team is responsible for STA methodology and signoff, design automation, internal and external EDA tools, and design analysis and optimization platforms.
What you'll do
- Enable and support a design analytics platform to analyze power, performance, area, and quality across products. - Collaborate closely with core and SOC design teams on methodology enablement and analysis. - Work with static timing analysis (STA) methodology and signoff flows across digital designs. - Interface with design automation, optimization platforms, and internal and external EDA tools.
What you'll need
- Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design, verification, validation, integration, or related work experience (or Master's with 3+ years, or PhD with 2+ years). - Experience with ASIC/VLSI design tools and flows. - Strong programming skills in Python. - Hands-on experience with static timing analysis (STA) tools, such as PrimeTime and Tempus.
Nice to have
- Software architecture understanding to develop platforms at scale. - Familiarity with GenAI models (such as LLMs like GPT or Llama) and their application in real-world solutions. - Experience designing and developing agentic AI systems. - Experience with version control tools like Perforce or Git. - Experience with place & route tools and an understanding of the ASIC RTL-GDSII design flow.
Skills: design analytics platform, ASIC/VLSI design tools, static timing analysis, RTL-GDSII flow, place & route
This role has been open 156 days — well above the 68-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
701
|
Median days open
68 d
|
Median salary
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (701 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 701 |
| Open roles in the wider Physical Implementation family | 171 | 1489 · 109 employers |
| Median days open | 75 d | 68 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: design analytics platform, ASIC/VLSI design tools, static timing analysis, RTL-GDSII flow, place & route
Who's hiring in this category
- Cadence Design Systems · 154 open roles · median 151 d
- Synopsys · 62 open roles · median 42 d
- Micron Technology · 44 open roles · median 51 d
- GlobalFoundries · 39 open roles · median 25 d
- Qualcomm (this employer) · 38 open roles · median 75 d
- Keysight Technologies · 34 open roles · median 78 d
How we counted: 701 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.