$121,900 - $195,000 USD yearly
Bring up complex ASIC IP and SoC designs using Cadence Palladium hardware acceleration and UVM verification.
Originally posted 7 November 2026 by the employer.
About the role
This role brings up complex ASIC IP and SoC designs on Cadence Palladium emulation platforms, converting the RTL database into emulation-ready models and executing high-speed hardware acceleration. You will also support core pre-silicon verification using UVM-based simulation and debugging.
What you'll do
- Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems, handling clocking/memory overrides and full-chip bring-up.
- Partner with firmware engineering teams to enable early FW bring-up on Palladium, mapping memory spaces and configuring virtual debuggers like JTAG to boot bootloaders, drivers, and operating systems.
- Perform traditional pre-silicon verification tasks using SystemVerilog and UVM, authoring test cases, developing monitors/checkers, and debugging RTL anomalies.
- Diagnose and root-cause hardware, testbench, and environment issues across both simulation and emulation environments using hardware-debugging features.
- Build and maintain automated scripts to compile the RTL database, launch Palladium regressions, and manage database hand-offs between design release teams and emulation.
What you'll need
- Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of hardware description or verification experience, or a Master’s Degree with 6+ years of relevant experience.
- Experience with hardware description languages (Verilog / SystemVerilog) and hardware synthesis concepts for emulation mapping.
- Experience in pre-silicon verification with SystemVerilog and UVM.
- Experience building and maintaining automated scripts for compiler tools and regression workflows.
Nice to have
- Deep hands-on experience with the Cadence Palladium enterprise emulation platform (e.g., Palladium Z1/Z2 or newer systems).
- Proven experience with UVM (Universal Verification Methodology) simulation frameworks, assertion-based testing (SVA), and metric-driven coverage closure.
- Expertise in Python, Perl, Bash, or Tcl to parse log files, automate compiler tools, and manage massive regression databases.
- Solid understanding of AMBA subsystem protocols (AXI, AHB, APB) and processor interfaces to configure memory and clock domains inside the emulator.
Skills: Palladium, Emulation, UVM, SystemVerilog, RTL
More semiconductor jobs: Broadcom jobs · Verification engineer jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1350
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (1350 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 1350 |
| Open roles in the wider Digital Design & Verification family | 78 | 3524 · 120 employers |
| Median days open | 24 d | 58 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Palladium, Emulation, UVM, SystemVerilog, RTL
Who's hiring in this category
- Qualcomm · 118 open roles · median 49 d
- Apple · 114 open roles · median 10 d
- NVIDIA · 105 open roles · median 71 d
- AMD · 87 open roles · median 67 d
- Synopsys · 75 open roles · median 51 d
- SiFive · 57 open roles · median 65 d
How we counted: 1350 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 7 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.