ASIC Design STA Engineer - CA, San Jose, United States
Originally posted 17 April 2026 by the employer.
Contribute to large SoC timing constraints across multiple physical blocks and over 300 clock domains.
About the role
AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs featuring multiple physical blocks and over 300 clock domains. Responsibilities center on building and verifying timing constraints across complex hierarchical designs.
What you'll do
- Develop complex multi-mode / multi-corner timing constraints compatible with RTL and signoff. - Maintain RTL quality metrics in complex, hierarchical designs and automate these processes. - Implement pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure quality handoff for STA checks. - Collaborate with CAD on pre-production synthesis (Design Compiler) and STA (PrimeTime) workflows. - Apply SDC expertise, EDA tool proficiency, and TCL-based scripting in EDA environments and standalone Linux TCL shells.
What you'll need
- Experience in SDC development and debugging for hierarchical SoC designs. - Proficiency in TCL-based scripting in EDA tool environments and standalone Linux TCL shells. - Familiarity with front-end (RTL) processes as well as back-end (Synthesis and P&R) processes. - Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related field.
Nice to have
- Hands-on experience building timing constraints for IPs, blocks, and full-chip implementation in flat and hierarchical flows. - Experience with EDA tools including Synopsys Design Compiler, PrimeTime, Spyglass, and Fishtail. - Prior experience writing custom TCL QC and QoR checks using DC/PT object attributes, queries, and filters. - Experience analyzing timing reports to identify design- and constraints-related issues.
Skills: SDC, STA, Timing Constraints, Primetime, TCL
This role has been open 184 days — well above the 65-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 63 | 673 |
| Open roles in the wider Physical Implementation family | 90 | 1491 · 109 employers |
| Median days open | 27 d | 65 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SDC, STA, Timing Constraints, Primetime, TCL
Who's hiring in this category
- Qualcomm · 124 open roles · median 48 d
- AMD (this employer) · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 17 d
- Synopsys · 37 open roles · median 39 d
- NVIDIA · 36 open roles · median 67 d
- Broadcom · 35 open roles · median 104 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.