$225,000 - $350,000 USD yearly
About the role
As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron AI’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve PPA and schedule goals.
What you'll do
- Define and document microarchitecture for complex IP blocks/subsystems.
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with Physical Design on floorplan and timing closure.
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
- Mentor junior engineers in design techniques, methodology, and problem-solving.
What you'll need
- BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Proven track record of leading designs from specification through microarchitecture, RTL, and signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
- Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
- Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.
- Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.
Nice to have
- Background in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning).
- Formal verification/SVA expertise for property checking and design assertions.
- Experience with low-power design techniques (clock-/power-gating, UPF/CPF).
- Collaboration experience with cocotb/UVM for checkers and reference model co-development.
- Familiarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows.
Skills: Microarchitecture, SystemVerilog RTL, DFT integration, PPA metrics, high-speed memory interfaces
More semiconductor jobs: RTL design jobs · Austin jobs
This role has been open 68 days — slightly above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Positron AI | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1096 |
| Open roles in the wider Digital Design & Verification family | 7 | 3525 · 120 employers |
| Median days open | 42 d | 64 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: Microarchitecture, SystemVerilog RTL, DFT integration, PPA metrics, high-speed memory interfaces
Who's hiring in this category
- Qualcomm · 139 open roles · median 73 d
- AMD · 94 open roles · median 50 d
- Synopsys · 90 open roles · median 51 d
- NVIDIA · 47 open roles · median 64 d
- NXP Semiconductors · 45 open roles · median 107 d
- Analog Devices · 41 open roles · median 54 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.