Applied Research Engineer, Chip Design
$192,000 - $356,500 USD yearly
Apply LLMs, coding agents, and agentic systems to ASIC design flows using Nemotron foundation models.
Originally posted 23 July 2026 by the employer.
About the role
This role focuses on applied research at the intersection of AI and ASIC design. You will apply large language models, coding agents, and agentic systems directly to chip design flows including RTL generation, verification, and PPA optimization.
What you'll do
- Apply LLMs, coding agents, and agentic systems to core ASIC design problems including RTL generation, design and formal verification, and PPA prediction and optimization.
- Build robust data generation pipelines, synthetic data, and evaluation methodologies to measure and benchmark working automation systems.
- Integrate coding agents and agentic AI into EDA and validation flows, covering simulation, regressions, waveform and log analysis, and script generation.
- Build models and research harnesses on top of open-source foundations, iterating from prototype to production deployment.
- Partner with the internal Nemotron team to improve models with domain-specific ASIC design data, feedback, and post-training.
What you'll need
- MS or PhD or equivalent experience in Computer Science, Electrical/Computer Engineering, or a related field.
- 8+ years of industry experience.
- Domain and technical expertise in front-end ASIC (design, verification, timing) combined with project experience applying agentic AI to chip design and optimization problems.
- Hands-on experience building LLM-based agents or AI tooling, covering context engineering, tool integration, orchestration, failure analysis, and evaluation.
- Experience with custom model training, fine-tuning, or post-training (SFT, RLHF/DPO) over proprietary technical data.
- Experience building and maintaining infrastructure using Docker, Slurm, and CI/CD.
- Proven experience presenting and explaining complex technical work.
Skills: AI and ASIC design, LLMs, RTL generation, Design and formal verification, EDA
More semiconductor jobs: NVIDIA jobs · EDA tools engineer jobs · California jobs
This role has been open 100 days — well above the 31-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
83
|
Median days open
31 d
|
Category median salary (all employers)
$208k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (83 roles · 28 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 83 |
| Open roles in the wider Physical Implementation family | 97 | 1547 · 111 employers |
| Median days open | 34 d | 31 d (+3 d vs this employer) |
| Median salary (USD postings) | — | $208k |
Skills observed across this category: AI and ASIC design, LLMs, RTL generation, Design and formal verification, EDA
Who's hiring in this category
- NVIDIA (this employer) · 11 open roles · median 31 d
- NXP Semiconductors · 10 open roles · median 89 d
- Keysight Technologies · 7 open roles · median 31 d
- Qualcomm · 6 open roles · median 5 d
- Synopsys · 6 open roles · median 9 d
- Cadence Design Systems · 5 open roles · median 84 d
How we counted: 83 open EDA/CAD Engineering (AI EDA Design) roles from 28 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.