Analog SerDes Architect - Saint-Sulpice, Switzerland
Kandou
Saint-Sulpice, Switzerland
18 days ago
Analog & Mixed-Signal Design
About the role
This role involves developing and maintaining system-level models for serial communication links and defining block-level specifications for transceivers.
What you'll do
- Implement, document, and maintain software for system-level modeling of serial communication links in MATLAB, Python, and C++.
- Work with system architects to budget the link and define block-level specifications of the transceiver.
- Collaborate with analog, digital, and verification teams to support design and verification processes.
What you'll need
- Good knowledge of control theory and digital algorithms.
- Demonstrated skills in implementing signal-processing algorithms.
- Understanding of the building blocks of a digital communication link and factors impacting link performance.
- Proficient in at least one of C++, MATLAB, or Python/NumPy.
- Familiarity with git version-control system and fundamentals of software engineering (unit-testing, profiling).
- Familiarity with analog circuit simulators (SPICE/SPECTRE).
Nice to have
- Familiarity with SerDes link components and clock recovery circuits.
- 5+ years of experience in semiconductor, telecommunications, or mathematical/scientific software industry.
- Experience with system-level simulation of digital communication systems (experience in SerDes links).
- Experience working with geographically dispersed teams.
Skills: system-level modeling, serial communication links, transceiver, signal-processing algorithms, SerDes
Market context
This role has been open 139 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Kandou | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 6 | 217 |
| Median days open | 98 d | 91 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: system-level modeling, serial communication links, transceiver, signal-processing algorithms, SerDes
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.