Analog/Mixed Signal ASIC Design Engineer

Originally posted 29 January 2026 by the employer — open 224 days.

About the role

This role involves designing high-speed, high-performance, and low-power mixed-signal IPs for Qualcomm's products. The focus will be on mixed-signal IPs such as SerDes, DDR, PLL, DAC, ADC, and sensors.

What you'll do

• Work in the analog design team for schematic capture and simulations.
• Participate in architecture definition and analog/digital design partitioning.
• Perform schematic capture and simulations using the Cadence Virtuoso tool suite.
• Collaborate with cross-functional teams, including layout and digital teams.
• Work with the testing team for silicon bringup and debugging.

What you'll need

• Master's degree in Electrical Engineering or related field.
• Demonstrated interest in analog circuit design through coursework or work experience.
• Experience with ASIC design tools such as Cadence Virtuoso.
• 2+ years of experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET.
• 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).

Nice to have

• Several years of industry experience in analog integrated circuit/system design.
• Experience as a high speed analog designer of mixed-signal IPs, such as CTLE, CDR, PLL RXAFE, PLL, DAC, ADC.
• Familiarity with Matlab and Python.
• Good understanding of architecture, system, and integration aspects for mixed-signal.
• Good understanding of design for yield and production challenges with high speed serial links.
• Good understanding of Signals and Systems.
• Sampled Domain signal processing experience.

Skills: analog design, schematic capture, Cadence Virtuoso, high speed analog, mixed-signal IPs, silicon bringup