$135,000 - $180,000 USD yearly
Originally posted 24 March 2025 by the employer — open 535 days.
Join a team focused on silicon photonics and high-speed transceiver design.
About the role
This role involves developing high-speed analog transceiver solutions for optical and wireline communication systems. You will contribute to designs that interface with silicon photonics elements.
What you'll do
- Support micro-architecture development with chip architects by conducting feasibility studies
- Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits
- Document design simulations and verifications towards formal design reviews
- Drive block-level floorplan, mask design views, and their reviews
- Run post-layout and mixed-signal top-level simulations to validate integration
- Define production and bench-level test plans
- Validate the performance of the circuits in the lab
What you'll need
- MS with 6+ years of industry experience, OR Ph.D. with 3+ years of industry experience with a focus on optical or wireline transceiver design
- Experience designing in either GHz-speed RF or GHz-speed broadband analog design
- Experience with Tx/Rx equalization techniques and circuits
- Familiarity with SERDES architectures and implementations
- Solid understanding of CMOS device characteristics, noise, mismatch, linearity, and design trade-offs
- Experience with Cadence Design Environment
Nice to have
- Experience designing Analog-Front-End blocks for transceiver circuits such as trans-impedance amplifiers (TIA) and Tx Driver
- Knowledge of 3D Electro-Magnetic (EM) simulation tools
- Experience with testing and validating high-speed analog/mixed-signal circuits
- Experience interfacing with silicon photonic modulators (MZM, Ring)
- Successful track record in delivering analog/mixed-signal IPs with 1st-time success while meeting tight schedules
Skills: high speed analog transceiver, optical and wireline communication, SERDES architectures, silicon photonics, TIA, Tx Driver
This role has been open 178 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lightmatter | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 100 d | 91 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high speed analog transceiver, optical and wireline communication, SERDES architectures, silicon photonics, TIA, Tx Driver
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.