Analog Design, Staff Engineer
Originally posted 7 September 2026 by the employer.
About the role
This role involves designing and optimizing analog and mixed-signal building blocks within SerDes designs.
What you'll do
- Ensure analog sub-block performance adheres to SerDes standards and architecture specifications.
- Identify and refine circuit implementations for optimal power, area, and performance targets.
- Propose design and verification strategies using simulator features.
- Oversee physical layout to minimize parasitics, device stress, and process variation.
- Partner with digital RTL engineers on verification of calibration, adaptation, and control algorithms for analog circuits.
- Take ownership of analog and mixed-signal building blocks integrated into a larger SerDes design.
What you'll need
- MSc with 4+ years of SerDes/High-Speed analog design experience.
- Familiarity with transistor-level circuit design of fundamental analog and mixed-signal building blocks.
- Silicon-proven experience implementing circuits for analog and mixed-signal building blocks.
- Design experience with SerDes sub-circuits, including receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC.
- Experience optimizing CMOS layout to minimize parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (circuit techniques, layout) and design for reliability (electro-migration, IR, aging).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
Skills: SerDes, high-speed analog design, mixed-signal building blocks, CMOS layout, electrical characterization
This role has been open 21 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
238
|
Median days open
78 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (238 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 238 |
| Open roles in the wider Analog & Mixed-Signal family | 36 | 1385 · 107 employers |
| Median days open | 44 d | 78 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes, high-speed analog design, mixed-signal building blocks, CMOS layout, electrical characterization
Who's hiring in this category
- AMD · 27 open roles · median 66 d
- Synopsys (this employer) · 25 open roles · median 46 d
- Qualcomm · 20 open roles · median 57 d
- Cadence Design Systems · 18 open roles · median 180 d
- Micron Technology · 11 open roles · median 75 d
- Apple · 10 open roles · median 12 d
How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.