Analog Design, Sr Staff Engineer - 17998
Originally posted 9 July 2026 by the employer — open 63 days.
Work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP.
About the role
This role involves the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of an analog and mixed-signal R&D team developing high-speed analog integrated circuits in the latest FinFET process nodes.
What you'll do
- Design and propose advanced algorithms to calibrate and adapt transceivers.
- Identify and refine circuit implementations to achieve optimal power, area, and performance targets.
- Develop and maintain SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
- Own Analog Macro level design.
- Review SerDes standards and architecture documents to develop analog specifications.
- Oversee physical layout to minimize parasitics, device stress, and process variation.
What you'll need
- M.Sc. or Ph.D. in Electrical or Computer Engineering with 6+ years of SerDes/High-Speed analog design experience.
- Silicon-proven experience implementing circuits for the TX, RX, and Clock paths within a SerDes.
- Strong experience modeling circuits and systems in MATLAB/Simulink.
- Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
- Proficiency in analyzing link budgets for PAM4 high-speed serial links.
- Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
- Detailed design experience with several SerDes sub-circuits (e.g., receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC).
- Experience optimizing FinFET CMOS layout to minimize parasitic resistance and capacitance, and to reduce local device mismatch and proximity effects.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
Skills: Multi-Gbps NRZ & PAM4 SERDES, high-speed analog integrated circuits, FinFET process nodes, PCIe (128Gbps+), Ethernet (200Gbps+), link budgets
This role has been open 61 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 16 | 217 |
| Median days open | 53 d | 91 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Multi-Gbps NRZ & PAM4 SERDES, high-speed analog integrated circuits, FinFET process nodes, PCIe (128Gbps+), Ethernet (200Gbps+), link budgets
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys (this employer) · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.