Analog Design, Sr.Staff Engineer-15024
Originally posted 29 January 2026 by the employer — open 224 days.
About the role
This role involves the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will develop high-speed (>200Gbps) analog integrated circuits in FinFET process nodes.
What you'll do
- Own Analog Macro level design.
- Track and review the work of sub-block owners.
- Review SerDes standards and architecture documents to develop analog specifications.
- Identify and refine circuit implementations to achieve optimal power, area and performance targets.
- Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
- Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
- Mentor and review the progress of junior engineers.
What you'll need
- Advanced degree with 6+ years of SerDes/High-Speed analog design experience.
- In-depth familiarity with transistor level circuit design and sound CMOS design fundamentals.
- Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes.
- Experience in leading a small team of designers collaborating on building blocks of a Macro level design.
- Detailed design experience with several SerDes sub-circuits including receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC.
- Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (circuit techniques, layout) and design for reliability (electro-migration, IR, aging).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
Skills: high-speed serial communication, transceiver design, NRZ/PAM4 serial-link, SERDES modeling, lab validation
This role has been open 155 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 16 | 217 |
| Median days open | 53 d | 91 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed serial communication, transceiver design, NRZ/PAM4 serial-link, SERDES modeling, lab validation
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys (this employer) · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.