About the role

This role involves the design, modeling, and verification of custom analog designs for high-speed Serdes transceivers in advanced technology nodes.

What you'll do

Design and verify analog circuits to meet architecture specifications, following prescribed design and documentation flows.
Support and interact with customers on requirements, design specifications, performance results, and product delivery.
Support analog IP and chip level integration.
Collaborate with architects, technical leads, analog and digital design, layout, integration, verification, silicon validation, and quality teams.
Manage and complete designs to schedule using defined design process flows.
Report design status to the internal management team.

Master's or Ph.D. degree in Electronics or other relevant fields.
Minimum 5 years of experience in analog design and layout of key circuits in multi-gigabit serial data-link transceivers or RF multi tone communications such as equalizers, clock generators, clock and data recovery circuits, TISAR ADC's, serialisers and output drivers.
Expertise in design and layout of high-speed circuits such as oscillators, phase-locked loops, delay-locked loops, biasing, amplifiers, buffers, regulators, filters, ADC, DAC.
Skilled in the design of high speed analog serdes circuits including DFT, DFM and ESD protection, with deep knowledge of transistor and wireline communications fundamentals.
Understanding of layout approaches and design techniques used for high-speed and high precision circuits.
Advanced user of EDA tools for design and verification of analog circuits, preferably using the Cadence Virtuoso environment, including their use for simulation, parasitic extraction, electromagnetic modelling, EM/IR and reliability analysis as well as LVS and DRC.
Experience with modern semiconductor process technologies, preferably in finFet technology nodes.

Skills: analog serdes circuits, high speed analog, data-link transceivers, PLLs, data converters