AI Silicon Performance Modeling and Analysis Engineer
$141,910 - $232,190 USD yearly
Originally posted 31 October 2026 by the employer.
About the role
This role drives performance modeling, validation, and architectural analysis for AI silicon subsystems including communication fabrics, memory hierarchies, and interconnects. You will develop SystemC and TLM-based models to evaluate architectural tradeoffs and guide product decisions for AI accelerators and SoCs.
What you'll do
- Develop, maintain, and enhance SystemC/TLM-based performance models representing SoC fabrics, memory controllers, scale-up/scale-out interconnects, and data movement architectures.
- Define and execute validation plans, regression suites, and coverage methodologies to correlate modeled behavior against reference simulations and hardware measurements.
- Design and run performance studies across AI workloads to analyze bandwidth, latency, congestion, buffering efficiency, and resource utilization.
- Build Python-based workflows, performance dashboards, and visualization tools to process large simulation datasets and track architectural KPIs.
- Partner with architecture, stimulus generation, and silicon design teams to evaluate architectural tradeoffs and present data-backed recommendations to leadership.
What you'll need
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or Electronics Engineering.
- 6+ years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, or performance engineering.
- Direct software development experience in C++ and working proficiency in Python for automation, data processing, and analysis.
- Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
- Working knowledge of SoC architecture, including on-chip communication fabrics, NoC concepts, high-speed interconnects, and scale-up/scale-out communication architectures.
- Experience with memory subsystem architecture, including memory controllers, cache hierarchies, data movement, and bandwidth/latency bottleneck analysis.
Nice to have
- Experience with Network-on-Chip (NoC) architecture and interconnect performance analysis.
- Understanding of scale-up and scale-out architectures used in modern AI computing platforms.
- Familiarity with AI/ML workloads, large language models, distributed training, and inference environments.
- Experience building automated dashboards and reporting tools using Power BI, Tableau, Grafana, or Plotly.
- Experience with performance stimulus generation methodologies and workload characterization.
Skills: SystemC, TLM, performance modeling, NoC, C++, Python
More semiconductor jobs: Intel Corporation jobs · SoC design jobs · California jobs
This role has been open 0 days — well below the 73-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
484
|
Median days open
73 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (484 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 484 |
| Open roles in the wider Digital Design & Verification family | 100 | 3357 · 115 employers |
| Median days open | 53 d | 73 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: SystemC, TLM, performance modeling, NoC, C++, Python
Who's hiring in this category
- Qualcomm · 78 open roles · median 86 d
- NVIDIA · 62 open roles · median 74 d
- Apple · 48 open roles · median 21 d
- AMD · 39 open roles · median 61 d
- Arm Holdings · 30 open roles · median 4 d
- Micron Technology · 21 open roles · median 108 d
How we counted: 484 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 1 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.