AI Silicon, Design Verification
Originally posted April 3, 2026 by the employer. Relisted by the employer on November 14, 2026.
About the role
This role leads design verification for IP blocks and full-chip implementations from specification through tape-out. You will construct verification infrastructure from the ground up, deploying UVM and SystemVerilog testbenches for specialized AI hardware.
What you'll do
- Define, architect, and implement verification plans and test environments for IP blocks and full-chip designs from specification to tape-out.
- Build scalable, automated verification infrastructure and testbenches from scratch.
- Deploy UVM and SystemVerilog to execute constrained-random stimulus generation, coverage-driven verification, and assertions.
- Collaborate with digital and analog design teams, software teams, and systems teams to debug complex hardware/software interactions.
- Perform functional and code coverage analysis, debugging failures at the RTL and gate level to reach closure.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Minimum of 8 years of hands-on experience with advanced verification methodologies and languages, specifically UVM and SystemVerilog.
- Proven track record of developing and maintaining complex verification testbenches and automated test environments.
- Proficiency in scripting languages such as Python, Shell, or Bash for verification flow automation and result analysis.
- Strong familiarity with Linux operating systems and industry-standard EDA tools from Cadence and Synopsys.
Nice to have
- Master's degree or Ph.D. in Electrical Engineering or Computer Science, with an emphasis on computer architecture.
- Expert-level knowledge of UVM architecture and high-level behavioral modeling.
- Experience with modern AI-driven code generation tools.
Skills: AI silicon, design verification, UVM, SystemVerilog
More semiconductor jobs: Verification engineer jobs · Mountain View jobs
First seen in our index 110 days ago, well above the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Unconventional AI | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1412 |
| Open roles in the wider Digital Design & Verification family | 7 | 3639 · 123 employers |
| Median days since first seen | 110 d | 59 d (−51 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: AI silicon, design verification, UVM, SystemVerilog
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.