# AI/ML Silicon Accelerator Memory Architect

Originally posted 3 November 2026 by the employer.

About the role

You will define the end-to-end memory and data transport architecture for accelerators, spanning controller design, on-die networks, DMA engines, and compute scratchpads.

What you'll do

• Define multi-generation memory architecture and strategy across HBM, LPDDR, GDDR, DDR, on-die SRAM hierarchies, and scratchpads.
• Derive capacity, bandwidth, and latency requirements from AI workloads including model size, KV-cache growth, prefill versus decode, and MoE sparsity.
• Architect memory controllers and cache/scratchpad microarchitecture covering scheduling, address mapping, and QoS across compute, DMA, and host traffic.
• Define data transport paths from memory to compute blocks, covering on-die interconnect topology, flow control, deadlock avoidance, QoS, and pJ/bit energy budgets.
• Specify DMA, gather/scatter, layout-transform, and multicast engines that support data movement.
• Develop analytical and simulation-based models to evaluate architectural trade-offs and drive silicon realization.

What you'll need

• MSEE/MSCE or PhD in EE, CE, CS, or related field, or equivalent demonstrated architectural impact.
• 18+ years in ASIC/SoC architecture focused on memory systems and data movement for HPC or AI.
• Deep knowledge of memory subsystems including HBM, DDR/LPDDR/GDDR, controller architecture, cache coherency, memory consistency models, and tiered/pooled memory.
• Demonstrated ownership of data movement architecture including on-die interconnect, DMA/copy engines, buffer hierarchies, and dataflow to compute.
• Understanding of the latency, area, and power costs of protocols such as NVLink, UALink, RDMA, ARM CHI, UCIe, and PCIe.
• Strong performance modeling and system-level simulation background with command of latency, throughput, utilization, and scalability.

Skills: HBM, DMA, Interconnect, Memory Subsystems, SoC Architecture, AI Accelerator

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