AI for Smarter IP Design Workflows - VALBONNE (Sophia), France
Originally posted 16 September 2026 by the employer — open 3 days.
About the role
This internship focuses on applying Artificial Intelligence to improve engineering productivity within semiconductor IP design workflows. You will investigate how AI can enhance reporting, data analysis, visualization, and automation within the Memory IP R&D team.
What you'll do
- Explore how AI can improve IP design workflows and engineering productivity.
- Analyze engineering reports, logs, and validation results to identify opportunities for automation.
- Develop software prototypes using Python and AI technologies.
- Create clearer and more effective ways to visualize and present engineering data.
- Collaborate with engineers to understand challenges and evaluate proposed solutions.
What you'll need
- Interest in Artificial Intelligence and emerging technologies.
- Basic programming skills.
- Strong curiosity and willingness to learn.
- Problem-solving mindset and attention to detail.
- Good communication and teamwork skills.
Nice to have
- Exposure to data analysis or software development.
- Interest in semiconductor technologies or engineering workflows.
- Python programming skills.
Skills: AI, IP design workflows, engineering productivity, software prototypes, Python
This role has been open 3 days — well below the 53-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
48
|
Median days open
53 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (48 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 48 |
| Open roles in the wider Physical Implementation family | 198 | 1371 · 106 employers |
| Median days open | 26 d | 53 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: AI, IP design workflows, engineering productivity, software prototypes, Python
Who's hiring in this category
- NXP Semiconductors · 10 open roles · median 47 d
- Cadence Design Systems (this employer) · 6 open roles · median 26 d
- NVIDIA · 5 open roles · median 58 d
- Qualcomm · 4 open roles · median 46 d
- Micron Technology · 3 open roles · median 134 d
- Synopsys · 3 open roles · median 31 d
How we counted: 48 open EDA/CAD Engineering (AI EDA Design) roles from 20 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.