AI-Assisted Foundation IP Development Intern - Singapore
Originally posted 29 September 2026 by the employer.
About the role
Part of Foundation IP team on standard cell and memory compiler IP for edge AI SoCs — including using data analysis and ML to spot trends in characterization data and flag outliers early.
What you'll do
- Support circuit design, spice/Monte Carlo simulation and layout of standard cells
- Perform layout tasks (placement, routing, DRC/LVS cleanup) for foundation IP
- Characterize standard cells (timing, power, noise) across PVT corners
- Run characterization flows using tools like Liberate
- Analyze characterization data using Python (pandas, scikit-learn) to find trends and outliers
- Build simple predictive models to flag likely failures and reduce simulation runs
What you'll need
- Pursuing a BS in EE, CE, Microelectronics, or related field (rising Junior/Senior)
- Coursework in digital logic, Analog, AI/ML, data Science, VLSI, or semiconductor devices
- Basic understanding of circuit design and IC layout (DRC/LVS) concepts
- Working knowledge of Python and basic ML concepts (regression, clustering)
- Comfort working with large datasets
Nice to have
- Exposure to layout/schematic tools (Virtuoso, Calibre) or characterization tools (Liberate, Tempus)
- A class project applying ML to engineering or scientific data
- Interest in low-power IP for edge AI/IoT
Skills: standard cell, memory compiler IP, characterization data analysis, ML to spot trends, layout, DRC/LVS
This role has been open 3 days — well below the 80-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
690
|
Median days open
80 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ambiq Micro | All employers we track in this specialty (690 roles · 77 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 690 |
| Open roles in the wider Physical Implementation family | 2 | 1436 · 108 employers |
| Median days open | 3 d | 80 d (−77 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: standard cell, memory compiler IP, characterization data analysis, ML to spot trends, layout, DRC/LVS
Who's hiring in this category
- Cadence Design Systems · 168 open roles · median 160 d
- Synopsys · 49 open roles · median 39 d
- NVIDIA · 41 open roles · median 69 d
- Micron Technology · 40 open roles · median 110 d
- Qualcomm · 36 open roles · median 70 d
- GlobalFoundries · 28 open roles · median 47 d
How we counted: 690 open EDA/CAD Engineering (EDA Tools) roles from 77 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.