$26 - $47 USD hourly
About the role
This role involves working with the platform team on an agentic platform that helps engineers debug and close mixed-signal verification.
What you'll do
- Implement and evaluate agent workflows for verification tasks.
- Connect agents to mixed-signal artifacts such as testbenches, sim logs, waveforms, and coverage.
- Build scripts, APIs, or UI pieces used by the team.
- Track quality and report results.
What you'll need
- Enrolled in a BS or MS program in computer science, electrical or computer engineering, or a related field.
- Programming experience (Python preferred).
- Interest in LLMs/agents and/or chip design and verification.
- Ability to debug code and communicate results clearly.
Nice to have
- Coursework or projects in circuits, digital design, or verification.
- Git and Linux.
- Exposure to SystemVerilog, Verilog-AMS, UVM, or analog simulation.
- Experience with LLM tooling, RAG, or agent frameworks.
Skills: agent workflows, mixed-signal artifacts, testbenches, sim logs, UVM
More semiconductor jobs: Verification engineer jobs · Irvine jobs
This role has been open 44 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Skyworks | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1345 |
| Open roles in the wider Digital Design & Verification family | 14 | 3525 · 120 employers |
| Median days open | 137 d | 58 d (+79 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: agent workflows, mixed-signal artifacts, testbenches, sim logs, UVM
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.