Advanced SerDes & Analog/Mixed-Signal IC Design Intern – Summer 2027
Originally posted 23 October 2026 by the employer.
About the role
Upscale is developing high-speed connectivity solutions for AI infrastructure and data centers, with summer interns working on advanced SerDes and analog/mixed-signal integrated circuit design. Focus areas span high-speed ADC design and modeling, foundation IP development, AI-driven circuit design, and ultra-low-jitter PLL design and modeling.
What you'll do
- Collaborate with engineers to investigate circuit and system-level design problems across SerDes architectures.
- Develop analytical models, behavioral simulations, and circuit-level simulations to evaluate new architectures and design approaches.
- Build scripts and tools to automate simulation, data analysis, optimization, and design workflows.
- Explore algorithms and circuit techniques to improve performance, power efficiency, robustness, and design productivity.
- Present technical findings, simulation results, and design recommendations to the engineering team.
- Contribute to circuit implementation, verification, characterization, or silicon measurement activities where appropriate.
What you'll need
- Currently pursuing an M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- Strong fundamentals in analog and mixed-signal circuit design, communication systems, signal processing, or related areas.
- Experience with circuit simulation, numerical analysis, or engineering computation.
- Proficiency in Python, MATLAB, or similar tools for modeling, automation, and data analysis.
Nice to have
- Coursework, research, or project experience in AI/ML applications in EDA, circuit design, or engineering optimization.
- Experience with high-speed ADCs, data converters, or receiver architectures.
- Experience with PLLs, clock generation, phase noise, jitter analysis, or DTC/TDC-based digital PLLs.
- Experience with high-speed SerDes, wireline transceivers, or high-speed communication systems.
- Familiarity with SPICE-based circuit simulators, MATLAB/Python modeling, RTL, or digital signal processing.
- Experience with optimization algorithms, machine learning, behavioral modeling, or automated verification.
Skills: SerDes, Analog/Mixed-Signal, IC Design, Silicon
More semiconductor jobs: Signal integrity jobs · California jobs
This role has been open 6 days — well below the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
244
|
Median days open
72 d
|
Category median salary (all employers)
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Upscale AI | All employers we track in this specialty (244 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 244 |
| Open roles in the wider Analog & Mixed-Signal family | 10 | 1527 · 106 employers |
| Median days open | 6 d | 72 d (−66 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: SerDes, Analog/Mixed-Signal, IC Design, Silicon
Who's hiring in this category
- Synopsys · 34 open roles · median 39 d
- AMD · 28 open roles · median 46 d
- Cadence Design Systems · 21 open roles · median 143 d
- Qualcomm · 19 open roles · median 72 d
- Micron Technology · 13 open roles · median 44 d
- Apple · 9 open roles · median 27 d
How we counted: 244 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.