$210,000 - $315,000 USD yearly
Lead 2.5D/3D advanced package design and methodology deployment for HPC and Datacenter multi-die products using TSMC 3Dblox, silicon interposers, and HBM integration.
Originally posted 6 November 2026 by the employer.
About the role
As a Principal Engineer, you will build and lead a 2.5D/3D Advanced Package Design team within CHS to support high-performance compute (HPC) and Datacenter products. You will direct package architecture, physical design implementation, verification, and tapeout flows using silicon interposers, silicon bridges, chiplets, and HBM.
What you'll do
- Build, manage, and mentor a 2.5D/3D advanced package design team covering package architects, physical design engineers, methodology developers, and CAD engineers.
- Own the strategy, roadmap, implementation, qualification, and deployment of 2.5D/3D package design flows for complex multi-die products.
- Lead implementation of packages using silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, hybrid-bonded or vertically stacked die, and HBM.
- Evaluate and deploy foundry and EDA 3DIC solutions, including TSMC 3Dblox-compatible methodologies, data-exchange flows, and signoff frameworks.
- Define and govern package verification and signoff criteria covering connectivity, DRC, DFM, ERC, LVS-equivalent checks, package extraction, SI/PI, thermal, and mechanical reliability.
- Partner with silicon architecture, SoC physical design, DFT, SI/PI, thermal, mechanical, board, and foundry/OSAT partners to drive concurrent chip-package-board-system co-design.
What you'll need
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, or related field with 8+ years of packaging design/technology experience (or Master's with 7+ years, or PhD with 6+ years).
- Experience building and leading advanced package design, 3DIC methodology, package CAD, or physical design engineering teams.
- Hands-on expertise with 2.5D/3D integration structures, including silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, HBM integration, chiplets, micro-bumps, and hybrid bonding.
- Deep familiarity with 3DIC EDA ecosystems from Cadence, Siemens EDA, Synopsys, or Ansys, including TSMC 3Dblox concepts, assembly description, and constraint management.
- Strong understanding of package-level SI/PI, thermal-mechanical stress, and electromagnetic effects for interfaces such as HBM, UCIe, PCIe, DDR, and high-speed SerDes.
- Experience with scripting and automation workflows using Python, Tcl, Perl, shell, APIs, and version control systems.
Nice to have
- Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science, or related field with 15 years of semiconductor package design or 3DIC methodology experience.
- Experience delivering production packages integrating compute SoCs or chiplets with HBM for AI, HPC, Datacenter, or networking products.
- Hands-on experience with tools including Cadence Innovus, Integrity 3D-IC, Allegro Package Designer (APD), Virtuoso, and Siemens Calibre 3DSTACK.
- Proven track record integrating foundry reference flows and assembly-description frameworks like TSMC 3Dblox into internal design, analysis, verification, and tapeout environments.
Skills: 2.5D/3D, Silicon Interposer, HBM, 3Dblox, UCIe
More semiconductor jobs: Qualcomm jobs · Advanced packaging jobs · San Diego jobs
First seen in our index 6 days ago, well below the 98-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
44
|
Median days since first seen
98 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (44 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 44 |
| Median days since first seen | 120 d | 98 d (−22 d vs this employer) |
| Median salary (USD postings) | n/a | $206k |
Skills observed across this category: 2.5D/3D, Silicon Interposer, HBM, 3Dblox, UCIe
Who's hiring in this category
- Marvell Technology · 7 open roles · median 51 d
- Micron Technology · 6 open roles · median 158 d
- AMD · 4 open roles · median 56 d
- Intel Corporation · 4 open roles · median 57 d
- NVIDIA · 4 open roles · median 92 d
- Qualcomm (this employer) · 4 open roles · median 128 d
How we counted: 44 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Days are counted from when our index first saw each posting, not from the employer's original posting date.