3D Heterogeneous Integration Development Intern (Summer 2027) - USA - New York - Malta, United States
$20 - $40 USD yearly
Originally posted 8 October 2026 by the employer.
About the role
This internship focuses on advanced packaging and process-integration development. The role involves contributing to advancements in wafer-to-wafer hybrid bonding, die-to-wafer hybrid bonding, through-silicon via/through-oxide via (TSV/TOV), and interposer technologies.
What you'll do
- Plan and perform design of experiments (DOEs) using internal tooling and external partners.
- Analyze and interpret engineering data from experiments, process optimizations, and characterization activities.
- Develop or support process models for advanced packaging and integration performance.
- Assist engineers with daily integration, process-development, documentation, and technical problem-solving.
- Collaborate with process, materials, equipment, characterization, and external partner teams.
- Summarize experimental results and communicate technical findings and recommended next steps.
What you'll need
- Actively pursuing a Bachelor’s or Master’s in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science, or related field.
- Overall GPA of at least 3.0.
- Fluency in English (written and verbal).
- Ability to travel up to 10%.
- Ability to work at least 40 hours per week during the internship.
Nice to have
- Prior related internship or co-op experience.
- Demonstrated prior leadership experience.
- Interest in leveraging AI tools and emerging technologies.
- Project management skills.
- Strong written and verbal communication skills.
- Strong planning and organizational skills.
- Currently pursuing a PhD in Engineering or related field.
- Experience with advanced semiconductor packaging, semiconductor integration, hybrid bonding, TSV/TOV, interposers, design of experiments, or engineering data analysis.
- Availability for a six-month co-op assignment.
Skills: 3D Heterogeneous Integration, hybrid bonding, TSV, interposer technologies, process-integration development
This role has been open 2 days — well below the 45-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
66
|
Median days open
45 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (66 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 66 |
| Median days open | 102 d | 45 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Skills observed across this category: 3D Heterogeneous Integration, hybrid bonding, TSV, interposer technologies, process-integration development
Who's hiring in this category
- Micron Technology · 10 open roles · median 162 d
- AMD · 7 open roles · median 47 d
- Marvell Technology · 5 open roles · median 30 d
- Broadcom · 4 open roles · median 133 d
- GlobalFoundries (this employer) · 4 open roles · median 101 d
- Intel Corporation · 4 open roles · median 23 d
How we counted: 66 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 25 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.