2027 Internship - Formal Verification Engineer - Austin, Texas, United States
Originally posted 27 October 2026 by the employer.
About the role
Cirrus Logic is seeking an intern candidate for the Formal Verification team in Austin, TX, focused on applying formal verification to digital designs.
What you'll do
- Support the formal verification team to follow and improve defined methodology practices. - Develop test plans and verification methodologies to formally verify the microarchitecture and design. - Perform failure analysis and resolution, coverage analysis, and population. - Implement and improve functional and formal verification.
What you'll need
- Current enrollment in an MS or PhD program in Electrical or Computer Engineering, with full-time availability during the internship. - Knowledge in designing and implementing verification environments for module-level designs. - Proficiency in SystemVerilog. - Knowledge in formal property languages such as SVA and property-based model-checking. - Experience or knowledge in UVM or equivalent methodologies. - Familiarity with scripting languages such as Python, Perl, TCL, or Bash. - Knowledgeable in signal processing, analog, or digital design fundamentals.
Skills: formal verification, SystemVerilog, SVA, UVM
This role has been open 0 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 1268 |
| Open roles in the wider Digital Design & Verification family | 30 | 3359 · 116 employers |
| Median days open | 206 d | 67 d (+139 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: formal verification, SystemVerilog, SVA, UVM
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.