Yield Engineer
$100,000 - $122,000 USD yearly
Sustain 0.35 to 0.13um RFCMOS/SiGe BiCMOS processes through defectivity monitoring and in-line yield resolution.
About the role
You will sustain released semiconductor processing by monitoring in-line defectivity levels, resolving in-line yield issues, creating inspection recipes on defect-inspection tools, and providing engineering feedback to optimize the manufacturing process. The role focuses on developing and sustaining 0.35 to 0.13um RFCMOS/SiGe BiCMOS processes.
What you'll do
- Monitor in-line defectivity levels, resolve in-line yield issues, and create inspection recipes on defect-inspection tools.
- Investigate, identify, verify, and contain particulate contamination sources across Photolithography, Etch, Diffusion, Thin-films, CMP/Hivac, Copper Damascene, and Wet-cleans.
- Analyze defect-trend data, disposition problem wafers and lots, and correlate defectivity types and levels to product yield using statistical process control techniques.
- Perform analysis of in-line defectivity, E-Test, and Probe data to evaluate experiments and in-line fab trends.
- Interface with Process Technicians to verify responses to daily issues and assist with priority and held lots.
- Partner with Integration, Process, Equipment, and R&D teams to deliver functional yield enhancements through defect reduction.
What you'll need
- Bachelor’s degree in Materials Science, Chemistry, Electrical Engineering, Microelectronic Engineering, or Solid-State Physics (new graduates with BSEE considered).
- 3-5 years of yield/process engineering experience.
- Experience sustaining in-line defectivity monitoring tools such as KLA/AMAT defectivity monitoring tools and optical/SEM microscopes.
- Strong knowledge of in-line automatic defect inspection tool application, recipe setup, and troubleshooting.
- Strong knowledge in using Yield Analysis software and the direct application of statistical process control.
- Demonstrated knowledge of process engineering principles across 0.35 to 0.13um RFCMOS/SiGe BiCMOS platforms.
Nice to have
- Master's degree in a related technical discipline.
- Experience in Copper CMP.
- Six-Sigma certification.
Skills: sustaining processing, in-line defectivity levels, in-line yield issues, defect-inspection tools, statistical process control
More semiconductor jobs: Yield engineer jobs · California jobs
This role has been open 135 days — well above the 58-day median for Yield Engineering roles.
Yield Engineering · Yield Engineering
|
Open roles in category
217
|
Median days open
58 d
|
Category median salary (all employers)
$137k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tower Semiconductor | All employers we track in this specialty (217 roles · 37 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 217 |
| Median days open | 135 d | 58 d (+77 d vs this employer) |
| Median salary (USD postings) | — | $137k |
Skills observed across this category: sustaining processing, in-line defectivity levels, in-line yield issues, defect-inspection tools, statistical process control
Who's hiring in this category
- Micron Technology · 107 open roles · median 75 d
- Intel Corporation · 11 open roles · median 25 d
- Skyworks · 10 open roles · median 39 d
- STMicroelectronics · 9 open roles · median 38 d
- GlobalFoundries · 6 open roles · median 102 d
- Renesas Electronics · 6 open roles · median 67 d
How we counted: 217 open Yield Engineering (Yield Engineering) roles from 37 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.