Wireless PHY Design Verification Engineer
Architect verification environments for WiFi PHY digital systems spanning time- and frequency-domain processing and calibration engines.
About the role
As a Wireless PHY Design Verification Engineer, you will verify WiFi PHY digital systems spanning time/frequency-domain processing, hardware acceleration, calibration engines, and protocol implementation. You will own subsystem verification from test planning through coverage closure for high-rate, low-power, and multi-link wireless features.
What you'll do
- Architect verification strategies and test plans for WiFi PHY digital subsystems, hardware accelerators, and calibration engines.
- Build verification environments, testbenches, and constrained random scenarios using SystemVerilog and UVM.
- Bring up complex designs and debug simulation failures across time/frequency-domain processing blocks.
- Implement functional coverage models and assertions to achieve complete coverage closure.
- Apply verification analytics methodologies to support first-time-right silicon tapeouts.
What you'll need
- Minimum requirement of a bachelor's degree.
- Track record of several tapeout cycles of sophisticated designs.
- Experience verifying wireless, DSP, or digital communication systems.
- Knowledge of ASIC verification flows with SystemVerilog and UVM, including testbench architecture, scenario creation, and coverage-driven methodologies.
- Experience developing verification environments, bringing up complex designs, and debugging simulations.
- Experience with constrained random testing, functional coverage implementation, and assertion-based verification.
Nice to have
- Knowledge of IEEE 802.11 wireless protocols, Bluetooth, Cellular, or similar communication systems.
- Experience with applying or integrating System models utilizing DPIs.
- Understanding of DSP algorithms verification strategies (Bit / Cycle matching, Assertions).
- Experience with transaction-level modeling including packet-based approaches (scoreboarding, protocols).
Skills: Wireless PHY, SystemVerilog, UVM, DSP, Tapeout
More semiconductor jobs: Apple jobs · Verification engineer jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1293
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1293 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 93 | 1293 |
| Open roles in the wider Digital Design & Verification family | 176 | 3447 · 120 employers |
| Median days open | 13 d | 58 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Wireless PHY, SystemVerilog, UVM, DSP, Tapeout
Who's hiring in this category
- Qualcomm · 116 open roles · median 48 d
- NVIDIA · 104 open roles · median 70 d
- AMD · 86 open roles · median 64 d
- Apple (this employer) · 75 open roles · median 14 d
- Synopsys · 73 open roles · median 49 d
- SiFive · 60 open roles · median 62 d
How we counted: 1293 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.