Emulation Verification Engineer

Verify large Wireless SoCs by bringing mixed signal models and RTL onto the Palladium platform.

About the role

As an Emulation Verification Engineer, you will utilize emulation for verification of large Wireless SoCs. You will work on porting designs and bringing mixed signal models onto the Palladium platform, followed by executing detailed emulation testplans.

What you'll do

• Create, deploy, and support advanced emulation environments.
• Port designs and integrate mixed signal models onto the Palladium platform.
• Execute detailed emulation testplans for large Wireless SoCs.
• Collaborate across design and verification disciplines throughout the chip design process.

What you'll need

• BS degree with a minimum of 10 years of relevant industry experience.
• Experience with System Verilog, Verilog, or UVM.
• Experience in creating test benches from scratch at both Block and System Level.
• Experience in regression management and triaging.

Nice to have

• Experience with bring up, debugging, and verification in Emulation.
• Understanding of the tool flow from RTL to Emulation.
• Understanding of standard emulators (Palladium, Veloce, Zebu) or FPGA flows (Xilinx, Altera).
• Design Verification or Silicon Validation skills.
• Experience writing synthesizable SystemVerilog/Verilog code and SystemVerilog assertions.
• Experience with System Verilog verification environments including C/C++ DPI and UVM.
• Scripting experience in Perl, Python, or TCL.
• Hands-on usage of low-power methodologies, preferably UPF-based.
• Experience in UVM Acceleration.

Skills: emulation, SystemVerilog, UVM, test benches, regression management, debugging

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