Wireless Design Verification Engineer
Verify Radio digital controllers and RF subsystems spanning PLLs, DAC/ADC data paths, and power management for WiFi SoCs.
About the role
Apple's Wireless Connectivity team is seeking a Wireless Design Verification Engineer to verify Radio digital controllers and RF subsystems for WiFi SoCs. The role covers radio control and transceiver paths spanning PLLs, DAC/ADC data paths, power management, and co-existence mechanisms.
What you'll do
- Develop verification environments for complex radio control and transceiver paths spanning PLLs, DAC/ADC data paths, power management, and co-existence mechanisms.
- Collaborate with Design, RF, PHY, and Systems teams to understand radio specifications and create test strategies.
- Own subsystem verification from test planning through coverage closure.
- Build testbench components and scenarios that exercise radio control sequences and operating modes.
- Bring up designs in simulation and debug functional issues.
What you'll need
- Bachelor’s degree in a relevant technical field.
- Understanding of ASIC verification flows with SystemVerilog, including UVM testbench development, scenario creation, and RTL simulation.
- Experience developing verification environments, bringing up designs in simulation, and debugging functional issues.
- Experience with digital design fundamentals using Verilog or VHDL.
- Experience with scripting languages such as Python.
Nice to have
- Experience with digital controllers, subsystems, or data paths.
- Experience with constrained random testing, functional coverage implementation, UVM methodology, and assertion-based verification.
- Exposure to mixed-signal modeling concepts, including real-number modeling.
- Exposure to RF/analog system design such as LNAs, Mixers, PLLs, amplifiers, LDOs, or DAC/ADCs.
- Proficiency with Python, Perl, Bash, or similar scripting languages for automation.
Skills: SystemVerilog, UVM, RTL Simulation, Verilog, Python
More semiconductor jobs: Apple jobs · Verification engineer jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1293
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1293 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 93 | 1293 |
| Open roles in the wider Digital Design & Verification family | 176 | 3447 · 120 employers |
| Median days open | 13 d | 58 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, RTL Simulation, Verilog, Python
Who's hiring in this category
- Qualcomm · 116 open roles · median 48 d
- NVIDIA · 104 open roles · median 70 d
- AMD · 86 open roles · median 64 d
- Apple (this employer) · 75 open roles · median 14 d
- Synopsys · 73 open roles · median 49 d
- SiFive · 60 open roles · median 62 d
How we counted: 1293 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.