Wireless Design Verification Engineer
Verify Radio digital controllers and Digital+RF subsystems for WiFi SoCs spanning PLLs, DAC / ADC data paths, and transceiver controls.
About the role
Apple's Wireless Connectivity team is hiring a Wireless Design Verification Engineer to lead the verification of Radio digital controllers and Digital+RF subsystems for WiFi SoCs. The scope spans architecting verification environments for radio control and transceiver paths across PLLs, DAC / ADC data paths, power management, and co-existence mechanisms.
What you'll do
- Architect verification environments for complex radio control and transceiver paths covering PLLs, DAC / ADC data paths, power management, and co-existence mechanisms.
- Lead verification of Radio digital controllers and Digital+RF subsystems across Design, RF, PHY, Systems, and Integration teams.
- Develop verification strategies for radio-modeled subsystems to validate wireless operation across varied operating conditions.
- Build testbenches from scratch, develop verification plans, and execute coverage-driven verification through simulation bring-up.
What you'll need
- BS and a minimum of 10 years of relevant industry experience.
- Track record of verifying complex digital ASICs with successful silicon tapeouts.
- Expertise in ASIC verification flows with SystemVerilog and UVM, including testbench architecture, verification planning, and coverage-driven methodologies.
- Experience developing verification environments from scratch and bringing up complex designs in simulation.
- Experience with constrained random testing, functional coverage, and assertion-based verification.
Nice to have
- Experience verifying Radio digital controllers, DSPs, PLL control systems, or wireless transceiver subsystems.
- Exposure to RF/analog system designs such as LNAs, Mixers, PLLs, amplifiers, LDOs, and DAC / ADCs.
- Experience with digital + mixed-signal co-simulation using SystemVerilog analog behavioral models / DMS or similar real-number-modeling approaches.
- Exposure to Python or similar scripting for automation, analysis, or infrastructure.
Skills: SystemVerilog, UVM, ASIC, Constrained Random, Functional Coverage
More semiconductor jobs: Apple jobs · Verification engineer jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1293
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1293 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 93 | 1293 |
| Open roles in the wider Digital Design & Verification family | 176 | 3447 · 120 employers |
| Median days open | 13 d | 58 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, ASIC, Constrained Random, Functional Coverage
Who's hiring in this category
- Qualcomm · 116 open roles · median 48 d
- NVIDIA · 104 open roles · median 70 d
- AMD · 86 open roles · median 64 d
- Apple (this employer) · 75 open roles · median 14 d
- Synopsys · 73 open roles · median 49 d
- SiFive · 60 open roles · median 62 d
How we counted: 1293 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.