$109,700 - $175,500 USD yearly
Originally posted 11 November 2026 by the employer.
About the role
As a VLSI ASIC Verification Engineer on the silicon engineering team, you will own the functional verification of complex digital blocks and subsystems.
What you'll do
- Analyze micro-architectural specifications to create comprehensive verification plans, trace requirements, and identify edge/corner cases.
- Design and build modular, reusable verification environments and testbenches using SystemVerilog and Universal Verification Methodology (UVM).
- Develop constrained-random stimulus, functional coverage models, scoreboards, and reference models.
- Write SystemVerilog Assertions (SVA) to catch design violations early, run simulations, debug waveforms, and root-cause RTL-to-testbench mismatches.
- Drive functional and code coverage to 100% closure prior to tape-out.
- Maintain automated regression suites using scripting languages like Python, Perl, or Tcl.
What you'll need
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 8 years of hands-on experience in ASIC, SoC, or IP design verification.
- Deep proficiency in SystemVerilog and UVM architectures (agents, drivers, monitors, scoreboards, virtual sequences).
- Solid working knowledge of AMBA protocols (AXI, AHB, APB) and memory/DMA controllers.
- Proven track record in constrained-random verification, functional coverage closure, and assertion-based verification (SVA).
- Hands-on experience with simulation and debug tools such as Synopsys VCS, Cadence Xcelium/Incisive, Mentor/Siemens Questa, or Verdi.
- Scripting skills in Python, Tcl, or Perl for build-flow automation and regression management.
Nice to have
- Familiarity with formal verification tools and techniques.
- Hands-on verification experience with RISC-V, ARM, or x86 core or subsystem architectures.
- Understanding of processor pipelines, branch prediction, out-of-order execution, superscalar designs, and execution units (ALU/FPU).
- Familiarity with verifying complex memory hierarchies, including L1/L2 caches, cache coherency protocols (AMBA CHI / ACE), MMUs, and virtual memory management.
- Exposure to high-speed interfaces or external protocols (DDR, PCIe, NVMe, SATA, or SAS).
Skills: SystemVerilog, UVM, constrained-random, SVA, functional coverage
More semiconductor jobs: Broadcom jobs · Verification engineer jobs
First seen in our index 2 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 1412 |
| Open roles in the wider Digital Design & Verification family | 84 | 3617 · 122 employers |
| Median days since first seen | 27 d | 59 d (+32 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, constrained-random, SVA, functional coverage
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.