Verification Engineer
$130,100 - $176,000 USD yearly
Verify Cortex-A processor memory-system functional blocks using SystemVerilog, UVM, and formal verification methods.
Originally posted 30 October 2026 by the employer.
About the role
This role is part of the Chandler-based CPU design verification team within the global CPU group, verifying Cortex-A processor designs with a focus on memory-system functional blocks. You will apply simulation and formal verification techniques to verify complex design behavior and develop verification environments.
What you'll do
- Develop SystemVerilog UVM and formal verification environments and tests for block-level functional verification.
- Create and maintain verification plans for assigned functional blocks across engineering project phases.
- Generate and run tests on logic simulation models, investigating and debugging functional issues in RTL using simulation and debug tools.
- Define and implement functional and statistical coverage, improve testbenches, and drive coverage closure.
- Collaborate with design and architecture teams to understand CPU memory-system behavior and resolve verification issues.
What you'll need
- Practical experience in pre-silicon design verification, including developing and debugging verification environments for RTL designs.
- Knowledge of CPU memory-subsystem microarchitecture, including load/store functionality, L2 cache, and memory management units (MMUs).
- Experience applying simulation and/or formal verification methods to verify hardware functional units.
- Software engineering capability in object-oriented programming, data structures, and algorithms, with experience using SystemVerilog and UVM.
Nice to have
- Experience verifying high-performance CPU memory systems, including cache coherence, virtual memory, address translation, out-of-order execution, or result return.
- Knowledge of processor microarchitecture concepts such as register renaming, reservation stations, or processor pipelines.
- Experience building reusable UVM testbenches and applying functional coverage-driven verification methods.
- Experience with software engineering practices including design patterns, profiling, unit testing, or programming in multiple languages.
- Bachelor's or master's degree in computer science, electrical engineering, computer engineering, or equivalent practical experience.
Skills: SystemVerilog, UVM, Formal Verification, Coverage Closure, RTL Simulation, Cache Coherence
More semiconductor jobs: Verification engineer jobs · Chandler jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1269
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1269 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 55 | 1269 |
| Open roles in the wider Digital Design & Verification family | 125 | 3324 · 115 employers |
| Median days open | 80 d | 58 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, Formal Verification, Coverage Closure, RTL Simulation, Cache Coherence
Who's hiring in this category
- Qualcomm · 112 open roles · median 43 d
- NVIDIA · 93 open roles · median 70 d
- AMD · 91 open roles · median 59 d
- Synopsys · 73 open roles · median 44 d
- Apple · 70 open roles · median 9 d
- SiFive · 56 open roles · median 83 d
How we counted: 1269 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.