Timing Engineer - San Jose, California, United States
$118,900 - $172,000 USD yearly
Originally posted 6 August 2026 by the employer.
About the role
This role supports timing analysis and closure activities for FPGA designs. You will gain hands-on experience with static timing analysis (STA), timing constraints, timing reports, timing optimization, and timing closure methodologies.
What you'll do
- Support static timing analysis (STA) for block-level and subsystem-level designs.
- Analyze timing reports to identify setup, hold, and other timing violations.
- Support the development, review, and validation of timing constraints for FPGA designs.
- Assist with timing closure activities by identifying critical paths and providing data-driven recommendations for optimization.
- Develop and maintain Python, Tcl, Perl, or similar scripts to automate timing analysis and improve engineering workflows.
- Work with Physical Design and RTL engineers to investigate timing issues and evaluate potential solutions.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 1+ year of relevant experience in timing analysis, digital design, semiconductor engineering, VLSI, ASIC, FPGA, or a related technical field.
- 1+ year of experience with digital logic, digital circuits, computer architecture, or integrated circuit design.
- 1+ year of experience or coursework involving timing analysis, simulation, or design verification.
- 1+ year of experience using Linux/Unix environments and technical scripting with Python, Tcl, Perl, or similar languages.
- Foundational understanding of digital timing concepts, setup and hold timing, clocking, and semiconductor design methodologies.
Nice to have
- Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Experience with static timing analysis (STA), timing constraints, timing reports, or timing closure.
- Familiarity with concepts such as setup and hold analysis, clock skew, clock uncertainty, critical paths, timing slack, and timing exceptions.
- Familiarity with multi-corner/multi-mode (MCMM) timing analysis and process, voltage, and temperature (PVT) variations.
- Familiarity with physical design concepts including synthesis, placement, routing, clock distribution, and design optimization.
Skills: timing closure, static timing analysis, STA, timing constraints, advanced process technologies
This role has been open 73 days — well above the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 659 |
| Open roles in the wider Physical Implementation family | 28 | 1441 · 110 employers |
| Median days open | 93 d | 60 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: timing closure, static timing analysis, STA, timing constraints, advanced process technologies
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.