Analog Layout Automation Engineer - Melbourne, United States
Originally posted 2 October 2026 by the employer.
About the role
This role focuses on contributing to the evolution of Analog/Mixed-Signal (AMS) circuits, including SerDes, PLLs, and sensors, by converting design concepts into silicon.
What you'll do
- Convert design concepts into silicon using advanced CAD tools to create high-performance analog and mixed-signal layouts.
- Review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues.
- Drive automation by developing scripts and improving workflows.
- Apply AI/ML for layout optimization, verification acceleration, advanced modeling, and intelligent quality metrics.
What you'll need
- BS and a minimum of 10 years relevant industry experience.
- Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python.
- Demonstrated ability to automate layout tasks, flows, and quality checks using scripting and CAD tools.
- High proficiency in interpreting physical verification reports, including DRC, ERC, and LVS.
Nice to have
- Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies.
- Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), loss functions, backpropagation, and optimization.
- Hands-on experience with PyTorch for model development and experimentation.
- Proven record in implementing high-quality analog layouts with tight device matching, low noise, and low power consumption.
- Familiarity with failure-prone circuit/layout structures, analog and DFM best practices.
- Strong proficiency in custom and standard-cell floor planning, hierarchical layout assembly, and physical integration.
- Understanding of image processing fundamentals, spatial representations, multi-channel image handling, segmentation, and object detection concepts.
- Technical understanding of IR drop, RC delay, electromigration, self-heating, coupling capacitance, and related reliability concerns.
- Experience using advanced Cadence Virtuoso features (XL, EAD, APR, Constraint Manager), and familiarity with Cadence Innovus.
- Experience with CAD automation workflows and PCell creation.
Skills: analog layout automation, SKILL, Perl, TCL, Python, Cadence Virtuoso, DRC, LVS
This role has been open 13 days — well below the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
683
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (683 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 683 |
| Open roles in the wider Physical Implementation family | 29 | 1449 · 108 employers |
| Median days open | 16 d | 73 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: analog layout automation, SKILL, Perl, TCL, Python, Cadence Virtuoso
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 169 d
- Synopsys · 63 open roles · median 39 d
- Micron Technology · 43 open roles · median 46 d
- Qualcomm · 38 open roles · median 73 d
- NVIDIA · 37 open roles · median 80 d
- GlobalFoundries · 33 open roles · median 36 d
How we counted: 683 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.