Test Engineer Various Levels - United States
Verification, Validation & Test
About the role
This role involves defining test plans, designing ATE hardware, and optimizing yield for semiconductor products at various stages from design to manufacturing.
What you'll do
- Define test plans and ensure test coverage with the design team.
- Design ATE hardware for NPI support, including Load Boards, probe cards, and interfaces.
- Manage products through their complete lifecycle from design to high volume manufacturing and sustaining support.
- Optimize yield, test time, and multi-site count.
What you'll need
- B.S./M.S. in Electrical Engineering or equivalent experience.
- Experience with Test coverage and DFT (Scan/ATPG/JTAG/BIST).
- Experience working with Local and offshore OSAT's.
- In-depth knowledge of Advantest V93k.
- Experience on Smartest, Redhat and GIT/SVN.
Nice to have
- Experience in DDR and High-speed Digital products.
Market context
This role has been open 44 days — well above the 22-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
506
|
Median days open
22 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Rambus | All employers we track in this specialty (506 roles · 72 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 506 |
| Open roles in the wider Silicon Validation & Test family | 4 | 2170 · 110 employers |
| Median days open | 61 d | 22 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 58 open roles · median 14 d
- Infineon Technologies · 40 open roles · median 35 d
- Renesas Electronics · 35 open roles · median 29 d
- AMD · 28 open roles · median 29 d
- Micron Technology · 27 open roles · median 31 d
- Qualcomm · 26 open roles · median 15 d
How we counted: 506 open Silicon Test Engineering (DFT Test) roles from 72 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.