Principal Test Development Engineer - Seremban, Negeri Sembilan, Malaysia
Originally posted 2 October 2026 by the employer.
This role focuses on advanced test solutions for Silicon (Si), Silicon Carbide (SiC), IGBT, and Gallium Nitride (GaN) technologies.
About the role
This role is responsible for defining and driving advanced test solutions for PSG's power semiconductor portfolio. The role provides strategic and technical leadership across wafer sort, die-level test, package final test, and power module test development.
What you'll do
- Provide technical leadership and mentorship for a global team of test development engineers.
- Drive test architecture decisions from product concept through high-volume manufacturing.
- Lead test development activities for new products including Power MOSFETs, IGBTs, SiC MOSFETs, SiC Modules, GaN Discrete Devices, Intelligent Power Modules (IPM), and Mixed-signal power products.
- Architect and develop wafer sort and final test solutions, designing and implementing test hardware, load boards, probe cards, interface boards, socket solutions, and automated test software.
- Define optimized multisite test strategies for cost reduction and throughput improvement.
- Lead test solution development for mixed-signal power products including Gate drivers, Driver + MOSFET combinations, Intelligent power devices, and Protection and control functions.
What you'll need
- Bachelor's degree in Electrical Engineering, Electronics Engineering, Physics, or equivalent.
- 10+ years of semiconductor test engineering experience.
- 5+ years of direct test development experience.
- Proven experience in power semiconductor products including Si, SiC, IGBT, and/or GaN technologies.
- Demonstrated technical leadership in NPI and production test deployment.
- Strong expertise in Wafer Sort Development, Final Test Development, Die-Level Characterization, Power Module Testing, Mixed-Signal Testing, Power Discrete Testing, Product Characterization, Statistical Analysis, Yield Optimization, and Root Cause Analysis.
Nice to have
- Master's degree.
- Experience with Teradyne ETS Series, Advantest Platforms, Cohu / Multitest, Accotest Platforms, or equivalent high-power semiconductor test systems.
- Programming experience in C/C++, Python, VBA / Automation Scripting, SQL.
- Data analytics experience with JMP, Minitab, Power BI, or Advanced Excel Analytics.
- Laboratory skills including Oscilloscope, Power Analyzer, Curve Tracer, Function Generator, High-Voltage Characterization Equipment, and Double-Pulse Test Systems.
- Experience with SiC MOSFET and module development, GaN device testing and characterization, Driver IC and analog mixed-signal product testing, Automotive and industrial power products, High-voltage power module test development, or AI-assisted engineering analytics.
- Experience in test methodology standardization across global manufacturing sites.
This role has been open 0 days — well below the 22-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
506
|
Median days open
22 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (506 roles · 72 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 506 |
| Open roles in the wider Silicon Validation & Test family | 86 | 2173 · 110 employers |
| Median days open | 9 d | 22 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 58 open roles · median 14 d
- Infineon Technologies · 40 open roles · median 35 d
- Renesas Electronics · 35 open roles · median 29 d
- AMD · 28 open roles · median 29 d
- Micron Technology · 27 open roles · median 31 d
- Qualcomm · 26 open roles · median 15 d
How we counted: 506 open Silicon Test Engineering (DFT Test) roles from 72 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.