Originally posted 3 November 2026 by the employer.
About the role
As a Technical Staff Engineer - Layout, you will be responsible for leading and executing automated place-and-route activities from floorplanning through GDSII tapeout. You will optimize design flows, develop physical design methodologies, and support execution through design signoff.
What you'll do
- Lead and execute automated place-and-route activities from initial floorplanning through final GDSII tapeout.
- Develop and implement physical design automation solutions for timing closure, QoR monitoring, ECO automation, data extraction, and physical verification analysis.
- Execute physical design activities including floorplanning and partitioning, power planning, power integrity, placement and routing optimization, and Clock Tree Synthesis (CTS).
- Perform timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff, including LEC/CLP checks.
- Collaborate with cross-functional engineering teams to resolve complex physical design challenges and optimize methodologies.
What you'll need
- 10+ years of experience in automated place and route and physical design using industry-standard tools and methodologies.
- Extensive experience across floorplanning, power integrity, placement and routing optimization, Clock Tree Synthesis (CTS), timing closure, signal integrity, and physical verification.
- Experience with design signoff checks, including LEC and CLP, alongside ECO implementation.
- Strong scripting and automation skills using Tcl, Perl, Python, or shell scripting to build custom physical design utilities and design closure workflows.
- Demonstrated background developing automation for data extraction, QoR monitoring, ECO automation, and physical verification analysis.
Skills: place and route, floorplanning, CTS, timing closure, physical verification, Tcl
More semiconductor jobs: Microchip Technology jobs · Physical design jobs
First seen in our index 10 days ago, well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
753
|
Median days since first seen
62 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (753 roles · 90 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 753 |
| Open roles in the wider Physical Implementation family | 26 | 1689 · 121 employers |
| Median days since first seen | 66 d | 62 d (−4 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: place and route, floorplanning, CTS, timing closure, physical verification, Tcl
Who's hiring in this category
- Qualcomm · 119 open roles · median 66 d
- AMD · 66 open roles · median 45 d
- Broadcom · 53 open roles · median 24 d
- NVIDIA · 46 open roles · median 85 d
- Synopsys · 44 open roles · median 43 d
- Apple · 32 open roles · median 8 d
How we counted: 753 open Physical Design (Physical Design) roles from 90 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.